FORMAL VERIFICATION OF BEHAVIOURAL TRANSFORMATIONS (SystemC to RTL)

ald_syn_cad · 发表于 2013-1-1 14:47:28

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本帖最后由 ald_syn_cad 于 2013-1-1 23:29 编辑

FORMAL VERIFICATION OF BEHAVIOURAL TRANSFORMATIONS DURING EMBEDDED SYSTEM DESIGN
Good when converting Syctemc to RTL by HLS.
Calypto SLEC do the same job.

lujunfeng111 · 发表于 2013-1-2 22:01:48

是书还是技术论文啊？

shengtuo1989 · 发表于 2013-1-2 22:04:21

这会是什么东西？咋没说明啊

ald_syn_cad · 发表于 2013-1-3 01:57:41

It's for formal equivalency checking between System Level designs (in SystemC) and their converted RTL forms when HLS tools like Catapult or Cadence Ctos are used.

pupukid · 发表于 2013-1-3 02:42:12

AD from EDA

chengweiquan · 发表于 2013-1-3 09:55:03

FORMAL VERIFICATION OF BEHAVIOURAL TRANSFORMATIONS DURING EMBEDDED SYSTEM DESIGN

tingyc · 发表于 2015-9-21 08:04:06

kankan

lvtv · 发表于 2016-10-21 16:06:52

看看~~~~~~~~~~~~~

Ryggeor · 发表于 2016-10-24 15:32:21

thnx!

[求助] FORMAL VERIFICATION OF BEHAVIOURAL TRANSFORMATIONS (SystemC to RTL)

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