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[招聘] 西安知名IC公司数字职位招聘

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发表于 2011-9-16 10:19:10 | 显示全部楼层 |阅读模式

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西安知名IC公司数字职位招聘

简历请发送:xianicjobintel@126.com
详情联系:xianicjobintel@126.com


职位及介绍:
后端设计工程师asic Backend Design Engineer (BE)

-设计验证工程师Design and Functional Verification Engineer (DFV)

-可测性设计工程师Design for Test Engineer (DFT)







Positions and requirement is as below:



1) 后端设计工程师ASIC Backend Design Engineer (BE)

Responsibilities:

1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.

2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.

3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).

4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.

5. Static Timing analysis (Prime Time) and setup/hold fix.

6. Formal Verification for equivalence checking (Formality).

7. Generation of fill structures according to technology requirements.

Requirements:

1. 2-4 years experience in backend design flow (APR) with proven SOC tape-out experience.

2. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.

3. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.

4. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.

5. Good analytical and debugging skills.

6. Good command of English.



2)设计验证工程师Design and Functional Verification Engineer (DFV)

Responsibilities:

1. Be responsible for the verification plan according the design-specification.

2. Work as an independent designer to check the design functionality and to cover all the design requirements at module level and sub-system level.

3. Test-bench and Test-case generation, simulation and debug to verify the design according to design specification and verification plan.

4. Test pattern generation and support the debug during chip test.

5. Work as interface with Front-End (Concept engineer) to optimize or review the design architecture.

6. Work as interface with Back-End (APR and STA Engineer) to optimize or review the design implementation (timing constrain, floor-plan, clock tree generation and so on).

7. verilog or Vhdl coding according to design specification or external/internal IP integration.

8. Support the post simulation with gate-level verilog or VHDL netlist.

Requirements:

1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of related working experience.

2. Experience with RTL coding and simulators (anyone of Modelsim, NC-sim, Specman).

3. Basic knowledge of script language (Perl, TCL, C-language and so on)

4. Basic knowledge of logic synthesis (Design Compiler), APR(IC-Compiler), Static Timing analysis (Prime-Time) and DFT.

5. Knowledge about 2G and 3G handset baseband Architecture, arm, AMBA Architecture is a big plus.

6. Team oriented, love to work in young, international and highly motivated teams.

7. Good command of English



3)可测性设计工程师Design for Test Engineer (DFT)

Responsibilities:

1. Participate in SoC level DFT architecture definition.

2. Implement DFT strategy for the SoC chips, cooperating with design team

3. Implement basic DFT schemes, including scan, boundary scan, MemBIST and LogicBIST.

4. Develop the high coverage and cost effective test patterns.

5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.

6. Support other teams for DFT related problems.

Requirements:

1. Either Bachelor or Master degree, 2+ years related experience required.

2. Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA

3. Good understanding of the General DFT methodology such as BIST, SCAN,JTAG and ATPG.

4. Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools

5. Proficient in Verilog/VHDL language

6. Be familiar with Shell/TCL/Perl program, or skilled in C program

7. Good English communication skills

8. Self-motivated and good team player
发表于 2011-9-16 12:56:39 | 显示全部楼层
mark.
发表于 2011-9-16 20:13:19 | 显示全部楼层
inter?   还某
发表于 2011-9-19 14:51:27 | 显示全部楼层
貌似Intel(西安)的职位!
发表于 2018-2-20 17:06:36 | 显示全部楼层
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