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发表于 2011-7-1 23:11:05
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Asic Design
Senior Level Design engineer
 Network protocol and system knowledge highly desirable (Ethernet, IP, ATM, SONET, DSL, EPON/GPON)
 Complete asic design cycle experience highly desirable
 Strong design/arch/testing capability of spec to rtl to product
 Strong understanding of large scale FPGA design/debugging
 Strong understanding of design trade off, speed/area trade off, optimization method, risk management
 Strong understanding of test coverage, test development and debug
 Strong skill in using Verilog/vcs, synthesis（DC）, timing analysis（PT)， DFT(Tetramax) tool
 Understanding of low power design technique
 Knowledge of Serdes, DDR memory, SOC/CPU, interfaces is big plus
 Documentation in English is highly desirable
Junior Level Design engineer
 Detail and discipline oriented, team work oriented
 Understanding of ASIC/FPGA design/verification flow
 Familiar with some of the EDA tool such as Verilog/VCS, Synthesis, Timing Analysis, DFT, FPGA is required
 Network protocol and system knowledge highly desirable (Ethernet, IP, ATM, SONET, DSL, EPON/GPON) |
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发表于 2011-6-10 19:21:02
