帮忙分析一个verilog综合占用资源报告

ch_5588 · 发表于 2011-6-6 13:14:48

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<a name=resourceUsage45>Resource Usage Report for TCAM_memory </a>

Mapping to part: xc3s1600efg320-4
Cell usage:
FDC          5 uses
FDCE          35 uses
FDE          2054 uses
GND          1 use
MUXCY          1 use
MUXCY_L       7 uses
MUXF5          512 uses
MUXF6          256 uses
MUXF7          128 uses
MUXF8          64 uses
RAM32X2S       3 uses
VCC          1 use
LUT1          6 uses
LUT2          38 uses
LUT3          3128 uses
LUT4          192 uses

I/O ports: 27
I/O primitives: 26
IBUF          14 uses
OBUF          12 uses

BUFGP       1 use

I/O Register bits:                0
Register bits not including I/Os: 2094 (7%)

RAM/ROM usage summary
Single Port Rams (RAM32X2S): 3

Global Clock Buffers: 1 of 24 (4%)

Total load per clock:
TCAM_memory|clk: 2097

Mapping Summary:
Total  LUTs: 3376 (11%)

Mapper successful!
Process took 0h:00m:57s realtime, 0h:00m:52s cputime
# Mon Jun 06 12:59:37 2011

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这是采用synplify综合后的Resource Utilization。请帮忙分析一下里面列举的都是什么呀？另外Mapping Summary:Total  LUTs: 3376 (11%) 这一个是包括Register和 Rams 吗？初学很多不懂，第一次用这个软件，望高手指点。谢谢！端午节快乐！