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本帖最后由 kscc0202121 于 2010-4-29 10:42 编辑
module counter(clk,clr,out);
input clk;
input clr;
output reg out;
reg[11:0] cnt;
always @(posedge clk or negedge clr)
begin
if(!clr)
begin
out <= 1'b0;
cnt <= 12'b0;
end
else begin
cnt <= cnt + 1'b1;
if(cnt[11:0]==12'h9db)
begin
cnt <= 12'h0;
out <= 1'b0;
end
else if(cnt[11:0]==12'h9db)
begin
out <= 1'b1;
end
end
end
endmodule |
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
port(
clk,clr : in std_logic;
dout : out std_logic
);
end counter;
architecture arch of counter is
signal cnt : unsigned(11 downto 0);
begin
process(clk,clr)
begin
if clr = '0' then
dout
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