High-Speed DRAM Controller Design

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Technical Note of Micron
Introduction
Multiple ways to design DRAM controllers exist, each having its own advantages and
disadvantages. The intent of this technical note is to identify and discuss five key areas of
DRAM controller design, including controller requirements, controller clock domains,
transmit circuits, capture circuits, strobe detection, and strobe delay circuits. As bandwidth
requirements have increased for high-speed DRAM memory systems, such as
high-speed networking, so, too, have the design challenges increased. For example, with
DDR3 data rates pushing 1.6 GHz, designing the logic interface has become particularly
challenging. And to deal with smaller data valid windows, many areas in the transmit
and receive circuits need to be enhanced.

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