FPGA/HDL Synthesis Simulation-Xilinx综合仿真好资料

zgq800712 · 发表于 2009-6-26 08:50:30

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在网上找译码器的资料，在xilinx无意间看到这个东西是网页板的；
第二章里面有Vhdl 和verilog对应的代码，同种电路举一反三，很受用... 对大家会很有帮助的

FPGA/HDL综合仿真好资料Xilinx Synthesis Technology (XST) User [email=Guide@Synthesis]Guide 与 Synthesis[/email] and Simulation Design Guide

Chapter 2
HDL Coding Techniques This chapter contains the following sections:

"Introduction" "Signed/Unsigned Support" "Registers" "Tristates" "Counters" "Accumulators" "Shift Registers" "Multiplexers" "Decoders" "Priority Encoders" "Logical Shifters" "Arithmetic Operations" "RAMs" "State Machines"
"Black Box Support"
Chapter 3
FPGA Optimization This chapter contains the following sections:

"Introduction" "Virtex Specific Synthesis Options" "Timing Constraints" "Macro Generation" "Log File Analysis" "Implementation Constraints"
"Virtex Primitive Support"

Chapter 4
CPLD Optimization
This chapter contains the following sections.
• “CPLD Synthesis Options”
• “Implementation Details for Macro Generation”
• “Log File Analysis”
• “Constraints”
• “Improving Results”

Chapter 5
Design Constraints
This chapter describes constraints, options, and attributes supported
for use with XST.
This chapter contains the following sections.
• “Introduction”
• “Setting Global Constraints and Options”
• “XST Constraints”
• “HDL Inference and Optimization”
• “FPGA Options”
• “CPLD Options”
• “Summary”
• “Implementation Constraints”
• “Third Party Constraints”
• “Constraints Precedence”

Chapter 6
VHDL Language Support
This chapter explains how VHDL is supported for XST. The chapter
provides details on the VHDL language, supported constructs, and
synthesis options in relationship to XST. The sections in this chapter
are as follows:
• “Introduction”
• “Data Types in VHDL”
• “Record Types”
• “Objects in VHDL”
• “Operators”
• “Entity and Architecture Descriptions”
• “Combinatorial Circuits”
• “Sequential Circuits”
• “Functions and Procedures”
• “Packages”
• “VHDL Language Support”

Chapter 7
Verilog Language Support
This chapter contains the following sections.
• “Introduction”
• “Behavioral Verilog Features”
• “Structural Verilog Features”
• “Parameters”
• “Verilog Limitations in XST”
• “Verilog Meta Comments”
• “Language Support Tables”
• “Primitives”
• “Verilog Reserved Keywords”

Chapter 8
Command Line Mode
This chapter describes how to run XST using the command line. The
chapter contains the following sections.
• “Introduction”
• “Launching XST”
• “Setting Up an XST Script”
• “Run Command”
• “Set Command”
• “Elaborate Command”
• “Time Command”
• “Example 1: How to Synthesize VHDL Designs Using Command
Line Mode”
• “Example 2: How to Synthesize Verilog Designs Using Command
Line Mode”

4-bit Unsigned Up Counter with Asynchronous Clear The following table shows pin definitions for a 4-bit unsigned up counter with asynchronous clear.

IO Pins

Description

C
Positive-Edge Clock
CLR
Asynchronous Clear (active High)
Q[3:0]
Data Output

VHDL Code Following is VHDL code for a 4-bit unsigned up counter with asynchronous clear.

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi; Verilog Code Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear.
module counter (C, CLR, Q); input C, CLR; output [3:0] Q; reg [3:0] tmp; always @(posedge C or posedge CLR) begin if (CLR) tmp = 4'b0000; else tmp = tmp + 1'b1; end assign Q = tmp; endmodule 4-bit Unsigned Down Counter with Synchronous Set The following table shows pin definitions for a 4-bit unsigned down counter with synchronous set.

IO Pins

Description

C
Positive-Edge Clock
S
Synchronous Set (active High)
Q[3:0]
Data Output

VHDL Code Following is the VHDL code for a 4-bit unsigned down counter with synchronous set.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, S : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C) begin if (C'event and C='1') then if (S='1') then tmp <= "1111"; else tmp <= tmp - 1; end if; end if; end process; Q <= tmp; end archi; Verilog Code Following is the Verilog code for a 4-bit unsigned down counter with synchronous set.
module counter (C, S, Q); input C, S; output [3:0] Q; reg [3:0] tmp; always @(posedge C) begin if (S) tmp = 4'b1111; else tmp = tmp - 1'b1; end assign Q = tmp; endmodule 4-bit Unsigned Up Counter with Asynchronous Load from Primary Input The following table shows pin definitions for a 4-bit unsigned up counter with asynchronous load from primary input.

IO Pins

Description

C
Positive-Edge Clock
ALOAD
Asynchronous Load (active High)
D[3:0]
Data Input
Q[3:0]
Data Output

VHDL Code Following is the VHDL code for a 4-bit unsigned up counter with asynchronous load from primary input.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, ALOAD : in std_logic; D : in std_logic_vector(3 downto 0); Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, ALOAD, D) begin if (ALOAD='1') then tmp <= D; elsif (C'event and C='1') then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi; Verilog Code Following is the Verilog code for a 4-bit unsigned up counter with asynchronous load from primary input.
module counter (C, ALOAD, D, Q); input C, ALOAD; input [3:0] D; output [3:0] Q; reg [3:0] tmp; always @(posedge C or posedge ALOAD) begin if (ALOAD) tmp = D; else tmp = tmp + 1'b1; end assign Q = tmp; endmodule 4-bit Unsigned Up Counter with Synchronous Load with a Constant The following table shows pin definitions for a 4-bit unsigned up counter with synchronous load with a constant.

IO Pins

Description

C
Positive-Edge Clock
SLOAD
Synchronous Load (active High)
Q[3:0]
Data Output

VHDL Code Following is the VHDL code for a 4-bit unsigned up counter with synchronous load with a constant.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, SLOAD : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C) begin if (C'event and C='1') then if (SLOAD='1') then tmp <= "1010"; else tmp <= tmp + 1; end if; end if; end process; Q <= tmp; end archi; Verilog Code Following is the Verilog code for a 4-bit unsigned up counter with synchronous load with a constant.
module counter (C, SLOAD, Q); input C, SLOAD; output [3:0] Q; reg [3:0] tmp; always @(posedge C) begin if (SLOAD) tmp = 4'b1010; else tmp = tmp + 1'b1; end assign Q = tmp; endmodule 4-bit Unsigned Up Counter with Asynchronous Clear and Clock Enable The following table shows pin definitions for a 4-bit unsigned up counter with asynchronous clear and clock enable.

IO Pins

Description

C
Positive-Edge Clock
CLR
Asynchronous Clear (active High)
CE
Clock Enable
Q[3:0]
Data Output

VHDL Code Following is the VHDL code for a 4-bit unsigned up counter with asynchronous clear and clock enable.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, CLR, CE : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then if (CE='1') then tmp <= tmp + 1; end if; end if; end process; Q <= tmp; end archi; Verilog Code Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear and clock enable.
module counter (C, CLR, CE, Q); input C, CLR, CE; output [3:0] Q; reg [3:0] tmp; always @(posedge C or posedge CLR) begin if (CLR) tmp = 4'b0000; else if (CE) tmp = tmp + 1'b1; end assign Q = tmp; endmodule 4-bit Unsigned Up/Down counter with Asynchronous Clear The following table shows pin definitions for a 4-bit unsigned up/down counter with asynchronous clear.

IO Pins

Description

C
Positive-Edge Clock
CLR
Asynchronous Clear (active High)
UP_DOWN
up/down count mode selector
Q[3:0]
Data Output

VHDL Code Following is the VHDL code for a 4-bit unsigned up/down counter with asynchronous clear.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, CLR, UP_DOWN : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then if (UP_DOWN='1') then tmp <= tmp + 1; else tmp <= tmp - 1; end if; end if; end process; Q <= tmp; end archi; Verilog Code Following is the Verilog code for a 4-bit unsigned up/down counter with asynchronous clear.
module counter (C, CLR, UP_DOWN, Q); input C, CLR, UP_DOWN; output [3:0] Q; reg [3:0] tmp; always @(posedge C or posedge CLR) begin if (CLR) tmp = 4'b0000; else if (UP_DOWN) tmp = tmp + 1'b1; else tmp = tmp - 1'b1; end assign Q = tmp; endmodule 4-bit Signed Up Counter with Asynchronous Reset The following table shows pin definitions for a 4-bit signed up counter with asynchronous reset.

IO Pins

Description

C
Positive-Edge Clock
CLR
Asynchronous Clear (active High)
Q[3:0]
Data Output

VHDL Code Following is the VHDL code for a 4-bit signed up counter with asynchronous reset.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi; Verilog Code There is no equivalent Verilog code, as Verilog does not support signed values.
No constraints are available.

第二篇
Synthesis and Simulation
Design Guide

Chapter 1
Introduction
This chapter provides a general overview of designing Field
Programmable Gate Arrays (FPGAs) with HDLs, and also includes
installation requirements and instructions. It includes the following
sections.
• “Architecture Support”
• “Overview of Hardware Description Languages”
• “Advantages of Using the Virtex-E FPGA Architecture”
• “Advantages of Using HDLs to Design FPGAs”
• “Designing FPGAs with HDLs”
• “Xilinx Internet Web Sites”

Chapter 2
Understanding High-Density Design Flow
This chapter describes the steps in a typical HDL design flow.
Although these steps may vary with each design, the information in
this chapter is a good starting point for any design. If necessary, refer
to the current version of the “Quick Start Guide” to familiarize yourself
with the Xilinx and interface tools. This chapter includes the
following sections.
• “Design Flow”
• “Entering your Design and Selecting Hierarchy”
• “Functional Simulation of your Design”
• “Synthesizing and Optimizing your Design”
• “Setting Constraints”
• “Evaluating Design Size and Performance”
• “Evaluating your Design for Coding Style and System Features”
• “Placing and Routing Your Design”
• “Timing Simulation of Your Design”
• “Downloading to the Device and In-system Debugging”
• “Creating a PROM File for Stand-Alone Operation”

Chapter 3
General HDL Coding Styles
This chapter contains HDL coding styles and design examples to help
you develop an efficient coding style. It includes the following
sections.
• “Naming and Labeling Styles”
• “Specifying Constants”
• “Choosing Data Type (VHDL only)”
• “Coding for Synthesis”
• “Implementing Latches and Registers”
• “Resource Sharing”
• “Reducing Gates”
• “Using Preset Pin or Clear Pin”

Chapter 4
Architecture Specific HDL Coding Styles for
XC4000XLA, Spartan, and Spartan-XL
This chapter includes coding techniques to help you improve
synthesis results. It includes the following sections.
• “Introduction”
• “Instantiating Components”
• “Using Boundary Scan (JTAG 1149.1)”
• “Using Global Clock Buffers”
• “Using Dedicated Global Set/Reset Resource”
• “Implementing Inputs and Outputs”
• “Encoding State Machines”
• “Implementing Inputs and Outputs”
• “Implementing Memory”
• “Implementing Multiplexers”
• “Using Pipelining”
• “Design Hierarchy”
• “Incremental Design (ECO)”

Chapter 5
Architecture Specific HDL Coding Styles for
Spartan-II, Virtex, Virtex-E, Virtex-II, and
Virtex-II Pro
This chapter includes coding techniques to help you improve
synthesis results. It includes the following sections.
• “Introduction”
• “Instantiating Components”
• “Using Boundary Scan (JTAG 1149.1)”
• “Using Global Clock Buffers”
• “Using Advanced Clock Management,”
• “Using Dedicated Global Set/Reset Resource”
• “Implementing Inputs and Outputs”
• “Encoding State Machines”
• “Implementing Operators and Generate Modules”
• “Implementing Memory”
• “Implementing Shift Register (Virtex/E/II and Spartan-II)”
• “Implementing Multiplexers”
• “Using Pipelining”
• “Design Hierarchy”
• “Modular Design and Incremental Design (ECO)”

Chapter 6
Simulating Your Design
This chapter describes the basic HDL simulation flow using the Alliance
software. It includes the following sections.
• “Introduction”
• “Adhering to Industry Standards”
• “Simulation Points”
• “VHDL/Verilog Libraries and Models”
• “Compiling HDL Libraries”
• “Running NGD2VHDL and NGD2VER”
• “Understanding the Global Signals for Simulation”
• “Simulating VHDL”
• “Simulating Verilog”
• “RTL Simulation Using Xilinx Libraries”
• “Timing Simulation”
• “Simulation Flows”
• “LMG SmartModels”
• “IBIS”
• “STAMP”

4–to–1 Multiplexer Design with Case Construct
• VHDL Example
-- CASE_EX.VHD
-- May 2001
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity case_ex is
port (SEL: in STD_LOGIC_VECTOR(1 downto 0);
A,B,C,D: in STD_LOGIC;
MUX_OUT: out STD_LOGIC);
end case_ex;
architecture BEHAV of case_ex is
begin
CASE_PRO: process (SEL,A,B,C,D)
begin
case SEL is
when “00” => MUX_OUT <= A;
when “01” => MUX_OUT <= B;
when “10” => MUX_OUT <= C;
when “11” => MUX_OUT <= D;
when others=> MUX_OUT <= '0';
end case;
end process; --End CASE_PRO
end BEHAV;

• Verilog Example
//////////////////////////////////////////
// CASE_EX.V //
// Example of a Case statement showing //
// A mux created using parallel logic //
// HDL Synthesis Design Guide for FPGAs //
// November 2000 //
//////////////////////////////////////////
module case_ex (A, B, C, D, SEL, MUX_OUT);
input A, B, C, D;
input [1:0] SEL;
output MUX_OUT;
reg MUX_OUT;
always @ (A or B or C or D or SEL)
begin
case (SEL)
2’b00:
MUX_OUT = A;
2’b01:
MUX_OUT = B;
2’b10:
MUX_OUT = C;
2’b11:
MUX_OUT = D;
default:
MUX_OUT = 0;
endcase
end
endmodule

scsdyxf · 发表于 2009-6-26 09:34:58

还有像你这样赚钱的啊？

小哥1900 · 发表于 2009-6-26 09:59:47

原帖由 scsdyxf 于 2009-6-26 09:34 发表

 登录/注册后可看大图

还有像你这样赚钱的啊？

人家辛辛苦苦上传资料上来怎么啦？招你惹你了？！！！而且楼主又没有把附件分割的七零八落的。你爱要不要。

yuelengyueming · 发表于 2009-6-26 10:18:57

安装ISE之后，这些都会有，在安装文件doc下。

zgq800712 · 发表于 2009-6-26 23:53:18

我没有装ISE，也没有用xilinx的东西；
多是用altera的；
我觉得xilinx的这2个东西不错，所以就发上来了；

xykdblct · 发表于 2011-4-5 01:08:12

很好，很好谢谢。。。

kebon22 · 发表于 2011-4-5 10:05:58

classic
thank u

girlb · 发表于 2011-4-6 16:16:20

Thanks very much

splum · 发表于 2011-4-6 17:13:26

下载下来学习学习

emiemi · 发表于 2012-2-6 23:27:24

下载下来学习学习

FPGA/HDL Synthesis Simulation-Xilinx综合仿真好资料

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

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