ASIC AND FPGA VERIFICATION：A GUIDE TO COMPONENT MODELING

scallion

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登录/注册后可看大图	登录/注册后可看大图 A Guide to Component Modeling To order this title, and for more information, click [url=http://nl.sitestat.com/elsevier/elsevier-com/s?st&ns_type=clickout&ns_url=[http://www.elsevierdirect.com/pr ... 80125105811&dmnum=CWS1]]here[/url] By Richard Munden, CEO, Free Model Foundry Included in series Systems on Silicon, Description Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the Vhdl/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today?s digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

[ 本帖最后由 scallion 于 2009-5-10 11:43 编辑 ]

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ouqingyv

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