Verifying complex, nanometer-scale ICs requires speed and efficiency, but current functional verification processes are fragmented, making it impossible to optimize either. Every design task has its own separate verification stage, resulting in numerous unique verification stages. Each stage has its own methodology, environment, tools, languages, models, user interfaces, APIs and, sometimes, specialized verification engineers. Engineers create almost everything from scratch at every stage, abandoning the preceding stage. The result is an expensive, slow, inefficient process that can allow critical bugs to reach silicon.
By unifying your verification methodology, you can address critical verification challenges, while maximizing overall speed and efficiency. The Cadence Incisive verification platform lets you develop a unified methodology, from system design to system design-in, for all design domains. The Incisive verification platform provides the tools, technologies, common user environment, and support needed to develop a unified methodology. The methodology encompasses all phases of the verification process and crosses all design domains.
Although the unified verification methodology produces the greatest gains in speed and efficiency when used in a complete top-down, integrated manner, you can use the appropriate parts of it for more application-specific designs. A complete top-down flow might not always be feasible for a number of different reasons, so the methodology is flexible in providing both top-down and bottom-up approaches to developing subsystems, while still providing an efficient top-down verification methodology.
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