The Design of an Asynchronous Microprocessor

kevinwjs

The page order is reversed in the document. It must be read backward.


Chapter 1 : Introduction .......................................................... 17
1.1 Motivation ....................................................................................... 17
1.1.1 Global synchronization .......................................................... 17
1.1.2 Performance ........................................................................... 18
1.1.3 Power consumption ............................................................... 18
1.2 Basic concepts ................................................................................. 19
1.2.1 Timing model ........................................................................ 19
1.2.2 Mode ...................................................................................... 19
1.2.3 Asynchronous signalling conventions ................................... 20
1.3 Objectives and thesis structure ........................................................ 22
1.3.1 Structure of the thesis ............................................................ 22
1.3.2 Author’s contribution ............................................................ 22
Chapter 2 : Related work ....................................................... 25
2.1 Automatic synthesis tools ................................................................ 25
2.1.1 CSP based compilation .......................................................... 25
2.1.2 Signal transition graphs ......................................................... 26
2.1.3 State machines ....................................................................... 27
2.2 Other related work ........................................................................... 27
2.3 Summary .......................................................................................... 28
2.3.1 Micropipelines ....................................................................... 28
2.3.2 AMULET group Micropipelines ........................................... 28
Chapter 3 : Micropipelines ................................................... 29
3.1 Basic concepts ................................................................................. 29
3.1.1 Event control modules ........................................................... 30
3.1.2 Metastability .......................................................................... 31
3.1.3 Event-controlled storage element .......................................... 32
3.2 Micropipelines ................................................................................. 33
3.2.1 A Micropipeline fifo ........................................................... 33
3.2.2 Micropipelines with processing ............................................. 34
3.3 Event control module structures ...................................................... 34
3.3.1 Exclusive OR gate ................................................................. 35
3.3.2 Muller C-Gate ........................................................................ 36
3.3.3 Transparent latch ................................................................... 37
Chapter 1 : Introduction .......................................................... 17
1.1 Motivation ....................................................................................... 17
1.1.1 Global synchronization .......................................................... 17
1.1.2 Performance ........................................................................... 18
1.1.3 Power consumption ............................................................... 18
1.2 Basic concepts ................................................................................. 19
1.2.1 Timing model ........................................................................ 19
1.2.2 Mode ...................................................................................... 19
1.2.3 Asynchronous signalling conventions ................................... 20
1.3 Objectives and thesis structure ........................................................ 22
1.3.1 Structure of the thesis ............................................................ 22
1.3.2 Author’s contribution ............................................................ 22
Chapter 2 : Related work ....................................................... 25
2.1 Automatic synthesis tools ................................................................ 25
2.1.1 CSP based compilation .......................................................... 25
2.1.2 Signal transition graphs ......................................................... 26
2.1.3 State machines ....................................................................... 27
2.2 Other related work ........................................................................... 27
2.3 Summary .......................................................................................... 28
2.3.1 Micropipelines ....................................................................... 28
2.3.2 AMULET group Micropipelines ........................................... 28
Chapter 3 : Micropipelines ................................................... 29
3.1 Basic concepts ................................................................................. 29
3.1.1 Event control modules ........................................................... 30
3.1.2 Metastability .......................................................................... 31
3.1.3 Event-controlled storage element .......................................... 32
3.2 Micropipelines ................................................................................. 33
3.2.1 A Micropipeline FIFO ........................................................... 33
3.2.2 Micropipelines with processing ............................................. 34
3.3 Event control module structures ...................................................... 34
3.3.1 Exclusive OR gate ................................................................. 35
3.3.2 Muller C-Gate ........................................................................ 36
3.3.3 Transparent latch ................................................................... 37
4.4.2 Condition code evaluation ..................................................... 76
4.4.3 Branch operations .................................................................. 77
4.5 Exception handling .......................................................................... 79
4.5.1 Hardware interrupts ............................................................... 79
4.5.2 Data abort overview .............................................................. 81
4.5.3 Data abort signalling .............................................................. 82
Chapter 5 : The register bank ............................................. 85
5.1 Register bank operation ................................................................... 85
5.1.1 Internal register structure ....................................................... 86
5.1.2 Register bank hazards ............................................................ 86
5.2 Write address storage ....................................................................... 87
5.2.1 An asynchronous register lock FIFO ..................................... 88
5.2.2 FIFO examination .................................................................. 89
5.2.3 Stalling reads ......................................................................... 90
5.3 Asynchronous register bank design ................................................. 90
5.3.1 Read and lock operations ....................................................... 90
5.3.2 Write operations .................................................................... 92
5.4 Additional features .......................................................................... 93
5.4.1 Dual lock FIFO ...................................................................... 93
5.5 Implementation ................................................................................ 94
5.6 Future enhancements - register bypassing ....................................... 96
5.6.1 Register through-passing ....................................................... 96
5.6.2 Last result re-use .................................................................... 97
Chapter 6 : Memory interface ............................................ 99
6.1 Address interface ............................................................................. 99
6.1.1 Load/Store multiple operation ............................................... 101
6.1.2 Changing the PC value .......................................................... 101
6.1.3 PC loop deadlock ................................................................... 102
6.1.4 PC pipeline ............................................................................ 103
6.1.5 Instruction overflow deadlock ............................................... 103
6.1.6 PCpipe implementation ......................................................... 105
6.1.7 Incrementer ............................................................................ 107
6.2 Data interface ................................................................................... 108
6.2.1 Data in ................................................................................... 108
Chapter 7 : Execution pipeline .......................................... 111
7.1 The multiplier .................................................................................. 111
Implementation ................................................. 117
8.1 Design flow ...................................................................................... 117
8.1.1 Verification of the design ...................................................... 117
8.2 Complete organization ..................................................................... 119
8.2.1 Datapath VLSI organization .................................................. 121
8.3 Silicon layout ................................................................................... 121
8.4 Test devices ..................................................................................... 123
Chapter 9 : Evaluation and further work ................... 125
9.1 Design characteristics ...................................................................... 125
9.1.1 Area overhead ........................................................................ 126
9.1.2 Pipeline organization ............................................................. 127
9.2 Further work .................................................................................... 128
9.2.1 Base technology ..................................................................... 128
9.2.2 Processor organization ........................................................... 129
9.2.3 Tools ...................................................................................... 129
9.2.4 Test ........................................................................................ 130
Chapter 10 : Conclusions ....................................................... 131
10.1 Micropipelines ............................................................................... 131
10.2 AMULET1 ..................................................................................... 132
10.3 An asynchronous future? ............................................................... 132
Chapter 11 : Bibliography ..................................................... 133
Appendix A: Timing characteristics ............................ 143
A.1 Measurement conditions ................................................................. 143
SPICE timings for: CALL2 ........................................................... 144
SPICE timings for: DMULLC2 ..................................................... 146
SPICE timings for: DXor/DXNor ................................................. 147
SPICE timings for: DWAIT2 ........................................................ 148
SPICE timings for: MULLC2R ..................................................... 149
SPICE timings for: MULLC2 ....................................................... 150
SPICE timings for: MULLC3R ..................................................... 151
SPICE timings for: TOGGLE ....................................................... 152
SPICE timings for: SELECT2 ....................................................... 155
SPICE timings for: TLTCHR ........................................................ 156
Appendix B: The arm processor ................................. 157
B.1 The ARM2 ...................................................................................... 157
B.1.1 Instruction set ........................................................................ 158
B.1.2 Organization .......................................................................... 159
B.2 The ARM6 ...................................................................................... 159

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machinecat-007

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CNC

是论文，不是书

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