Timing Analysis and Simulation for Signal Integrity Engineers [SI.2007]

drjiachen

Timing Analysis and Simulation for Signal Integrity Engineers (Prentice Hall Modern Semiconductor Design Series' Sub Series: PH Signal Integrity Library) (Hardcover)by Greg Edlund (Author)


Hardcover: 272 pages
Publisher: Prentice Hall PTR; 1 edition (November 1, 2007) Language: English ISBN-10: 0132365049 ISBN-13: 978-0132365048



Product Description
Every day, companies call upon their signal integrity engineers to make difficult decisions about design constraints and timing margins. Can I move these wires closer together? How many holes can I drill in this net? How far apart can I place these chips? Each design is unique: there’s no single recipe that answers all the questions. Today’s designs require ever greater precision, but design guides for specific digital interfaces are by nature conservative. Now, for the first time, there’s a complete guide to timing analysis and simulation that will help you manage the tradeoffs between signal integrity, performance, and cost.

Writing from the perspective of a practicing SI engineer and team lead, Greg Edlund of IBM presents deep knowledge and quantitative techniques for making better decisions about digital interface design. Edlund shares his insights into how and why digital interfaces fail, revealing how fundamental sources of pathological effects can combine to create fault conditions. You won’t just learn Edlund’s expert techniques for avoiding failures: you’ll learn how to develop the right approach for your own projects and environment.

Coverage includes
•  Systematically ensure that interfaces will operate with positive timing margin over the product’s lifetime–without incurring excess cost
•  Understand essential chip-to-chip timing concepts in the context of signal integrity
•  Collect the right information upfront, so you can analyze new designs more effectively
•  Review the circuits that store information in CMOS state machines–and how they fail
•  Learn how to time common-clock, source synchronous, and high-speed serial transfers
•  Thoroughly understand how interconnect electrical characteristics affect timing: propagation delay, impedance profile, crosstalk, resonances, and frequency-dependent loss
•  Model 3D discontinuities using electromagnetic field solvers
•  Walk through four case studies: coupled differential vias, land grid array connector, DDR2 memory data transfer, and PCI Express channel
•  Appendices present a refresher on SPICE modeling and a high-level conceptual framework for electromagnetic field behavior
Objective, realistic, and practical, this is the signal integrity resource engineers have been searching for.

About the Author

Greg Edlund’s career in signal integrity began in 1988 at Supercomputer Systems, Inc., where he simulated and measured timing characteristics of bipolar embedded RAMs used in the computer’s vector registers. Since then, he has participated in the development and testing of nine other high-performance computing platforms for Cray Research, Inc., Digital Equipment Corp., and IBM Corp. He has had the good fortune of learning from many talented engineers while focusing his attention on modeling, simulation, and measurement of IO circuits and interconnect components. A solid physical foundation and practical engineering experience combine to form a valuable perspective on optimizing performance, reliability, and cost.

drjiachen

Content

Chapter 1. Engineering Reliable Digital
Interfaces
A Sadly Familiar Tale
Power On
The Long Reach of Legacy Design
Reflections on a Near Disaster
Motivations to Develop a Simulation
Strategy
The Boundaries of Simulation Space

Chapter 2. Chip-to-Chip Timing
Root Cause
CMOS Latch
Timing Failures
Setup and Hold Constraints
Common-Clock On-Chip Timing
Setup and Hold SPICE Simulations
Timing Budget
Common-Clock IO Timing
Common-Clock IO Timing Using a
Standard Load
Limits of the Common-Clock
Architecture

Chapter 3. Inside IO Circuits
CMOS Receiver
CMOS Differential Receiver
Pin Capacitance
Receiver Current-Voltage
Characteristics
CMOS Push-Pull Driver
Output Impedance
Output Rise and Fall Times
CMOS Current Mode Driver
Behavioral Modeling of IO Circuits
Behavioral Model for CMOS Push-Pull
Driver
Behavioral Modeling Assumptions
Tour of an IBIS Model
IBIS Header
IBIS Pin Table
IBIS Receiver Model
IBIS Driver Model
Behavioral Modeling Assumptions
(Reprise)
Comparison of SPICE and IBIS Models
Accuracy and Quality of IO Circuit
Models

Chapter 4. Modeling 3D Discontinuities
Beyond Transmission Lines
Finite Difference Time Domain Method
Solo Flight in a 3D Field Solver
Coaxial Transmission Line
Boundary Conditions
Waveguide Ports
Stimulus Function
Mesh Density
Running the Solver
Port Signals
S-Parameters
Energy
Field Visualization
Coaxial Discontinuity
Formation of Reflection
S-Parameters and Their Explanation

Chapter 5. Practical 3D Examples
Coupled Differential Vias
Mechanical Drawings
Ports
Mesh Density
Sanity Check
Documentation
Pre-Flight Checklist
Land Grid Array Connector
Mechanical Trade-Offs
Electrical Characterization
3D Modeling Decisions
Test Card Design
Model-to-Hardware Correlation

Chapter 6. DDR2 Case Study
Evolution from a Common Ancestor
DDR2 Signaling
Write Timing
Read Timing
Get to Know Your IO
Off-Chip Driver
On-Die Termination
Rising and Falling Waveforms
Interconnect Sensitivity Analysis
Conductor and Dielectric Losses
Impedance Tolerance
Pin-to-Pin Capacitance Variation
Length Variation Within a Byte Lane
DIMM Connector Crosstalk
Vref AC Noise and Resistor Tolerance
Slope Derating Factor
Final Read and Write Timing Budgets
Sources of Conservatism
Assumptions

Chapter 7. PCI Express Case Study
High-Speed Serial Interfaces
Sensitivity Analysis
Ideal Driver and Lossy Transmission
Line
Differential Driver with De-Emphasis
Card Impedance Tolerance
3D Discontinuities
Channel Step Response
Crosstalk Pathology
Crosstalk-Induced Jitter
Channel Characteristics
Sensitivity Analysis Results
Model-to-Hardware Correlation
Reflections

Appendix A. A Short CMOS and SPICE Primer
MOSFETs
Two Basic CMOS Circuits
SPICE
Sample SPICE Input Deck
SPICE Transistor Models
SPICE Subcircuits

Appendix B. A Stroll Through 3D Fields
Four Poetic Equations
Charges at Rest
Steady-State Currents
The Non-Intuitive Force
Enter Time
Waves
Dropping a Few Dimensions
Endnotes
Index

drjiachen

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[ 本帖最后由 drjiachen 于 2008-10-25 00:01 编辑 ]

drjiachen

网速好慢啊

empwr

goreat book

empwr

thanks

seacanoesss

Timing Analysis and Simulation for Signal Integrity Engineers [SI.2007]

seacanoesss

Timing Analysis and Simulation for Signal Integrity Engineers [SI.2007]

seacanoesss

Timing Analysis and Simulation for Signal Integrity Engineers [SI.2007]

seacanoesss

Timing Analysis and Simulation for Signal Integrity Engineers [SI.2007]