Digital VLSI Design with Verilog(经典数字设计书)

henryliu

数字设计方面的书！
一直是从论坛下载资料，今天也作一次贡献。

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project.

In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs.

Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the accompanying CD-ROM. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.

A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.

Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parity and ECC), fifos, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are cover

[ 本帖最后由 henryliu 于 2008-10-17 18:05 编辑 ]

henryliu

第一部分的

henryliu

第二部分的，全书完毕！

gckdren

gckdren

henryliu

兄弟们，下载完毕请顶帖子！

开卷有益更要顶帖子！

feitengyu

这里已经有了
http://www.eetop.com.cn/bbs/viewthread.php?tid=114295&highlight=Digital%2BVLSI%2BDesign%2Bwith%2BVerilog

henryliu

那是另外一位仁兄上传的，应该是我的版本。