在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 23780|回复: 151

Advanced.ASIC.Chip.Synthesis.Using.Synopsys.Design.Compiler

[复制链接]
发表于 2008-4-27 08:04:16 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
CHAPTER 1: asic DESIGN METHODOLOGY 1
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.2
1.2.1
1.3
Traditional Design Flow
Specification and RTL Coding
Dynamic Simulation
Constraints, Synthesis and Scan Insertion
Formal Verification
Static Timing Analysis using PrimeTime
Placement, Routing and Verification
Engineering Change Order
Physical Compiler Flow
Physical Synthesis
Chapter Summary
2
4
5
6
8
10
12
13
16
17
11
viii
CHAPTER 2: TUTORIAL 19
2.1
2.2
2.3
2.3.1
2.3.2
2.4
2.5
Example Design
Initial Setup
Traditional Flow
Pre-layout Steps
Post-Layout Steps
Physical Compiler Flow
Chapter Summary
20
21
22
22
36
42
42
CHAPTER 3: BASIC CONCEPTS 45
3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.5
3.6
3.7
3.8
3.8.1
3.8.2
3.9
Synopsys Products
Synthesis Environment
Startup Files
System Library Variables
Objects, Variables and Attributes
Design Objects
Variables
Attributes
Finding Design Objects
Synopsys Formats
Data Organization
Design Entry
Compiler Directives
hdl Compiler Directives
VHDL Compiler Directives
Chapter Summary
45
48
48
49
51
51
52
53
54
55
55
56
57
58
60
61
CHAPTER 4: SYNOPSYS TECHNOLOGY LIBRARY 63
4.1
4.1.1
4.1.2
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.3
4.3.1
Technology Libraries
Logic Library
Physical Library
Logic Library Basics
Library Group
Library Level Attributes
Environment Description
Cell Description
Delay Calculation
Delay Model
64
64
64
65
65
66
66
71
74
74
Contents ix
4.3.2
4.4
4.5
Delay Calculation Problems
What is a Good Library?
Chapter Summary
76
77
79
CHAPTER 5: PARTITIONING AND CODING STYLES 81
5.1
5.2
5.2.1
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.5
5.5.1
5.5.2
5.6
Partitioning for Synthesis
What is RTL?
Software versus Hardware
General Guidelines
Technology Independence
Clock Related Logic
No Glue Logic at the Top
Module Name Same as File Name
Pads Separate from Core Logic
Minimize Unnecessary Hierarchy
Register All Outputs
Guidelines for FSM Synthesis
Logic Inference
Incomplete Sensitivity Lists
Memory Element Inference
Multiplexer Inference
Three-State Inference
Order Dependency
Blocking versus Non-Blocking Assignments in verilog
Signals versus Variables in VHDL
Chapter Summary
82
84
84
85
85
85
86
86
87
87
87
87
88
88
89
94
97
98
98
99
100
CHAPTER 6: CONSTRAINING DESIGNS 101
6.1
6.1.1
6.1.2
6.2
6.3
6.3.1
6.3.2
6.3.3
6.4
6.5
Environment and Constraints
Design Environment
Design Constraints
Advanced Constraints
Clocking Issues
Pre-Layout
Post-Layout
Generated Clocks
Putting it Together
Chapter Summary
102
102
107
114
116
117
118
119
120
122
x
CHAPTER 7: OPTIMIZING DESIGNS 125
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.6
Design Space Exploration
Total Negative Slack
Compilation Strategies
Top-Down Hierarchical Compile
Time-Budgeting Compile
Compile-Characterize-Write-Script-Recompile
Design Budgeting
Resolving Multiple Instances
Optimization Techniques
Compiling the Design
Flattening and Structuring
Removing Hierarchy
Optimizing Clock Networks
Optimizing for Area
Chapter Summary
125
129
131
131
132
134
135
137
139
139
141
144
145
148
148
CHAPTER 8: DESIGN FOR TEST 151
8.1
8.1.1
8.1.2
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
Types of DFT
Memory and Logic BIST
Boundary Scan DFT
Scan Insertion
Shift and Capture Cycles
RTL Checking
Making Design Scannable
Existing Scan
Scan Chain Ordering
Test Pattern Generation
Putting it Together
DFT Guidelines
Tri-State Bus Contention
Latches
Gated Reset or Preset
Gated or Generated Clocks
Use Single Edge of the Clock
151
152
153
153
154
157
158
161
162
164
165
166
167
167
167
168
169
Contents xi
8.3.6
8.3.7
8.3.8
8.4
Multiple Clock Domains
Order Scan-Chains to Minimize Clock Skew
Logic Un-Scannable due to Memory Element
Chapter Summary
169
170
170
173
CHAPTER 9: LINKS TO LAYOUT & POST LAYOUT OPT. 175
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.4
Generating Netlist for Layout
Uniquify
Tailoring the Netlist for Layout
Remove Unconnected Ports
Visible Port Names
Verilog Specific Statements
Unintentional Clock or Reset Gating
Unresolved References
Layout
Floorplanning
Clock Tree Insertion
Transfer of Clock Tree to Design Compiler
Routing
Extraction
Post-Layout Optimization
Back Annotation and Custom Wire Loads
In-Place Optimization
Location Based Optimization
Fixing Hold-Time Violations
Chapter Summary
177
177
179
180
180
181
182
183
183
183
188
192
194
194
199
200
202
203
205
209
CHAPTER 10: PHYSICAL SYNTHESIS 211
10.1
10.1.1
10.2
10.2.1
10.2.2
10.3
10.4
10.5
10.6
Initial Setup
Important Variables
Modes of Operation
RTL 2 Placed Gates
Gates to Placed Gates
Other PhyC Commands
Physical Compiler Issues.
Back-End Flow
Chapter Summary
212
212
213
213
216
220
221
223
223
xii
CHAPTER 11: SDF GENERATION 225
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.3
SDF File
SDF File Generation
Generating Pre-Layout SDF File
Generating Post-Layout SDF File
Issues Related to Timing Checks
False Delay Calculation Problem
Putting it Together
Chapter Summary
226
228
228
231
232
233
235
237
CHAPTER 12: PRIMETIME BASICS 239
12.1
12.1.1
12.1.2
12.1.3
12.2
12.2.1
12.2.2
12.2.3
12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.4
Introduction
Invoking PT
PrimeTime Environment
Automatic Command Conversion
Tcl Basics
Command Substitution
Lists
Flow Control and Loops
PrimeTime Commands
Design Entry
Clock Specification
Timing Analysis Commands
Other Miscellaneous Commands
Chapter Summary
240
240
240
241
242
243
243
245
245
245
246
250
256
259
CHAPTER 13: STATIC TIMING ANALYSIS 261
13.1
13.1.1
13.2
13.2.1
13.2.2
13.3
13.3.1
13.3.2
13.4
13.4.1
13.5
Why Static Timing Analysis?
What to Analyze?
Timing Exceptions
Multicycle Paths
False Paths
Disabling Timing Arcs
Disabling Timing Arcs Individually
Case Analysis
Environment and Constraints
Operating Conditions – A Dilemma
Pre-Layout
261
262
263
263
267
270
270
272
272
273
274
Contents xiii
13.5.1
13.5.2
13.6
13.6.1
13.6.2
13.6.3
13.7
13.7.1
13.7.2
13.7.3
13.7.4
13.8
13.8.1
13.8.2
13.8.3
13.8.4
13.9
Pre-Layout Clock Specification
Timing Analysis
Post-Layout
What to Back Annotate?
Post-Layout Clock Specification
Timing Analysis
Analyzing Reports
Pre-Layout Setup-Time Analysis Report
Pre-Layout Hold-Time Analysis Report
Post-Layout Setup-Time Analysis Report
Post-Layout Hold-Time Analysis Report
Advanced Analysis
Detailed Timing Report
Cell Swapping
Bottleneck Analysis
Clock Gating Checks
Chapter Summary
275
276
278
278
279
280
284
285
286
289
291
292
293
296
297
300
303
APPENDIX A 306
APPENDIX B 319
INDEX 321
Foreword

abbr_36117313e6eed05ef8cdff3e0a6ead5b.rar

2.14 MB, 下载次数: 1161 , 下载积分: 资产 -2 信元, 下载支出 2 信元

发表于 2008-6-24 02:14:53 | 显示全部楼层

                               
登录/注册后可看大图
发表于 2008-6-24 02:18:56 | 显示全部楼层
thanks
发表于 2008-8-2 15:51:46 | 显示全部楼层
Thanks for sharing!!
发表于 2009-6-25 06:20:09 | 显示全部楼层
thanx for sharing
发表于 2009-7-1 09:49:05 | 显示全部楼层

thanx for sharing

thanx for sharing
发表于 2009-7-2 22:16:29 | 显示全部楼层
这本书都好老了啊!!!!
发表于 2009-7-2 22:19:45 | 显示全部楼层
很好的资料 谢谢
发表于 2009-7-11 20:28:02 | 显示全部楼层
没有东西呀!!!
发表于 2009-8-17 10:53:25 | 显示全部楼层

下了看看

下了看看
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

×

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-3-29 20:25 , Processed in 0.039647 second(s), 10 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表