西安知名IC招聘，想回西安发展的朋友们注意了。

fy_muyangren · 发表于 2018-1-31 19:23:53

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朋友们，在西安待遇优于中兴。欢迎投简历到275246964@qq.com , 或者加qq具体聊。抱歉不能留电话。公司内部招聘，并非中介。

1. Front-end Engineer

Requirement：Either Bachelor or Master Degree, 2+ years related experience required; good knowledge of UVM/OVM/VMM; good knowledge of Verilog/C/C++/System C/SystemVerilog; strong ability of scripting languages such as Perl, Python, Makefile, C Shell; familiar with EDA tools, i.e. Synopsys VCS, Cadence IUS, Mentor QuestaSim, Spyglass; low-power design/implementation/simulation flow with UPF/CPF.

Location：Xian

2. DFT Engineer

Requirement：Either Bachelor or Master Degree, 2+ years related experience required; good knowledge of UVM/OVM/VMM; good knowledge of Verilog/C/C++/System C/SystemVerilog; strong ability of scripting languages such as Perl, Python, Makefile, C Shell; familiar with EDA tools, i.e. Synopsys VCS, Cadence IUS, Mentor QuestaSim, Spyglass; low-power design/implementation/simulation flow with UPF/CPF.

Location：Xian

3. Back-end Engineer

Requirement：Either Bachelor or Master Degree, 2+ years related experience required; good knowledge of UVM/OVM/VMM; good knowledge of Verilog/C/C++/System C/SystemVerilog; strong ability of scripting languages such as Perl, Python, Makefile, C Shell; familiar with EDA tools, i.e. Synopsys VCS, Cadence IUS, Mentor QuestaSim, Spyglass; low-power design/implementation/simulation flow with UPF/CPF.

Location：Xian

fy_muyangren · 发表于 2018-1-31 23:01:07

2.DFT

Requirement：Either Bachelor or Master degree, 1+ years related experience required; implement DFT strategy for the SoC chips, cooperating with design team; implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST; fluent Chinese and English, both verbal and written.
Location：Xian

3. Back-end

Requirement：Either Bachelor or Master degree, 2+ years related experience required; Work as technical expert to support technical team. Responsible for developing digital designs with emphasis on backend, including Floor-plan,power planning, Place, CTS and Route; Work with Front-end designers to optimise timing/area/power of the design implementation and perform static timing analysis; fluent Chinese and English, both verbal and written.