[转]ARM-compatible 32-bit RISC CPU Amber Study (1)

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转自：http://dv333.com/index.php/archives/161

Amber isARM-compatible 32-bit RISC processor. The Amber core is fully compatible with the ARM® v2a instruction set architecture (ISA) and is therefore supported by the GNU toolset. This older version of the ARM instruction set is supported because it is not covered by patents so can be implemented without a license from ARM.
Arch as below:
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The hello world simulation result:
Amber Boot Loader v20150406182528
j 0x00008000
Hello,DV World!
—————————————————————————-
Amber Core
> User FIRQ IRQ SVC
r0 0x00000010
r1 0x16000000
r2 0x00000000
r3 0x00000000
r4 0x0c008003
r5 0xdeadbeef
r6 0xdeadbeef
r7 0xdeadbeef
r8 0xdeadbeef 0xdeadbeef
r9 0xdeadbeef 0xdeadbeef
r10 0x00000011 0xdeadbeef
r11 0xf0000000 0xdeadbeef
r12 0x00001ed8 0xdeadbeef
r13 0x08000000 0xdeadbeef 0xdeadbeef 0x01ffffb0
r14 (lr) 0x00008020 0xdeadbeef 0xdeadbeef 0x600003fb
r15 (pc) 0x000084ac
Status Bits: N=0, Z=1, C=1, V=0, IRQ Mask 0, FIRQ Mask 0, Mode = User
—————————————————————————-
++++++++++++++++++++
Passed hello-dv-world 48324 ticks
++++++++++++++++++++
$finish called from file “vlog/tb/tb.v”, line 509.
$finish at simulation time 1208077500
Waveform:

                               
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代码下载：
http://dv333.com/index.php/archives/161

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