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PositionDescription:
Deliver/implementadvanced verification solutions by utilizing Cadence’s Incisive Verificationproduct portfolio. The engineer should be able to act as a strong team memberand contributor, leading team projects and initiatives. Exercise judgmentwithin generally defined practices and policies. Specificduties include: --Deepunderstanding on ASIC/SOC design flow --Excellentknowledge of advanced verification methodology like eRM/OVM/UVM –Familiarwith Cadence’s Incisive Plan to Closure Methodology (IPCM) --Proficiencyin System Verilog, System C and/or e (Specman) –Developingand using Verification Components (eVC,OVC,UVC,VIP) –Developingand using assertion based verification and formal analysis methods --Skilledin scripting language,such as Perl,C shell,Python,Makefile –Assessingthe project verification requirements –Operatingin a lead role regarding architecting and implementation of projectverification environment/solution. –Maycoordinate/lead others within the scope of a defined project
PositionRequirements: EssentialQualifications: -BS degree with 5+ years of applicable experience,MS degree with 4+ years ofapplicable experience in electrical engineering,microelectronics,comparableengineering science or solid state physics. -Essential that the individual demonstrates strong communication,verbal andwritten. Requires good communication skills in English.
DesirableQualifications: -A minimum of four years relevant experience in industry. -Will have demonstrated hands-on experience and expertise with Cadenceverification design tools or equivalent tools, flows and methodologies requiredto execute a verification project. -Will have demonstrated successful completion of 6+ verification projects as anindividual contributor -Will have DDR project verification experience
Any queries Please contactAnnie Song: 150 218 37144 |