张江招聘：前后端设计，IC验证等工程师

HR_Cissy

以下是我公司招聘中的部分职位，感兴趣的请投递到：hrsh02@viatech.com.cn工作地点：上海浦东张江
薪资待遇：面议
在这里，你可以学习和掌握与世界同步的核心技术，让你以后的职业生涯打下坚实的基础

招聘职位：1.职位名称：Audio System Engineer

职位描述：
【Department】SW
【Responsibilities】
-GPU kernel mode driver development and debug
-GLX/DRI driver development and debug
-GPU driver performance optimization
-Xserver DDX driver development and debug
- Related tool development and debug
【Requirements】
-MS or equivalent
-Solid C programming and debugging skills
-Be proficient in Linux device driver development
-Good understanding of 3D graphics algorithm, driver or application is a plus
-Familiar with Linux graphics framework, such as X11, mesa/DRI is a plus
-Familiar with Android Multimedia frame work
-Experience with Android Audio Flinger is highly desired.
-Familiar with Linux ALSA Driver architecture
-Familiar with audio and voice processing codecs including post processing effects highly desired but not required
-Familiar with Android Multimedia frameworks, APIs, audio, video and container formats

2.职位名称：Senior Compiler Engineer

职位描述：
【Department】Arch
【Responsibilities】
- Developing front-end and back-end compiler for the OpenCL in GPU processor.
- OpenCL conformance/benchmark/game/application debug, analyzing and performance tuning.
- Leading edge GPU parallel computing algorithm researching and designing.
【Requirements】
-MS or above in CS/CE/MATH
-Positive and responsible attitude for work
-Good communication skills
-Fluent in English: reading/writing
-Excellent C/C++ programming and debugging skills
-Compiler developing experience
【Preferred Qualifications】
-GCC or LLVM experience
-Knowledge in graphics shader language such as CUDA, OpenCL, D3D
-Assembly language development experience
-Linux gdb experience or Windows MS Visual Studio development experience

3.职位名称：FPGA Design Engineer


职位描述：
【Department】GPS
【Responsibilities】
-Working in the GPS team, developing high performance stand alone GPS/Compass (Beidou) receiver.
-Participate in the development of products from product specification to mass production.
-Setup the FPGA platform for system validation and test.
-Develop and maintain FPGA RTL codes.

【Requirements】
-MS and 3+ years for BS in Computer Science or Electronics Engineering.
-Solid knowledge on FPGA and related EDA tools, such as ISE, Quartus, Simplify
-Familiar with HDL, Verilog or VHDL, must have RTL coding experience
-Familiar with ARM based SoC design.
-Lab test and debugging skills to evaluate the prototype ICs for mass production
-Good English skill both in spoken and written

4.职位名称：Physical Design Engineer

职位描述：
【Responsibilities】
-Use mainstream EDA tools and advanced methodology to do IC physical layer design.
-Implement 40nm advanced process Multi-ten million gates hierarchical IC P&R and Timing complete solution.
-Use C Shell/Perl/Tcl to automate design flow.
【Requirements】
-MS or equivalent. Major in microelectronics or relative department.
-Have the experience of using Cadence, Synopsys backend tools.
-Familiar with Script programming, having physical synthesis, SI experience as a plus.
-Good communication and positive attitude.

5.职位名称：ASIC Verification Engineer

职位描述：
【Department】HW
【Responsibilities】
-Maintain/Optimize current verification environment/tools/scripts.
-Develop verification tools for different design phase (RTL coding, module verifying, integration& regression), for better RTL quality/test efficiency.
-Setup/Enhance the automated regression environment (regression management, reporting and bug tracing system)
-Incorporate reusability into verification environment infrastructure and push the verification methodology to greater technical depth.
【Requirements】
-Major in EE, CS or related, MS or BS Degree with 3+ years in verification related working experiences
-Familiar with Linux Environment (including shell's and linux tools), advanced on Verilog, C++, and scripts language (perl, Tcl)
-Versatile in any of the high level verification flow such as SystemVerilog, OVM(UVM), VMM, VERA, etc.
-Better understanding of Verification methodology and concepts, and knowledge of industry standard tools for verification
-Good understanding of Pre-Silicon design flows from Architecture, Design, Synthesis and Gate level Implementation till tape-out.
-Able to organize across different engineering teams, with strong problem solving skills, perseverance and ability to work under pressure.

HR_Cissy

已经陆续有收到同行们的简历了，职位还未close，感兴趣的快来投吧~

zhuyujun

一家不错的公司！

feng841210

简历2、3天前发过去了，还没面试通知啊，被cancel掉了啊？

strivenbu

S3吧 还是不错的

HR_Cissy

回复 3# zhuyujun


   谢谢！

oamp

周二电话沟通过一次，问了下薪水，是否没戏了？

cw佛学

回复 1# HR_Cissy

招IC analog layout engineer不哦？

feng841210

发了简历，直接没响应啊。。。。

HR_Cissy

回复 7# oamp


   请问你面试的什么职位？