C@dence.C-to-Sillion.CTOS.11 Linux

nerohark

                               
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At the core of Cadence system-level design solutions, Cadence® C-to-Silicon Compiler automatically generates synthesizable RTL starting from untimed C/C++/SystemC® with as little as 10% of the effort required using manual methods. C-to-Silicon Compiler has been architected from the ground up with four unique capabilities that deliver revolutionary advantages to hardware architects and RTL designers:

Embedded logic synthesis (ELS) enables parallel optimization of control and datapath logic, greatly enhancing the quality of results
Behavior-structure-timing (BST) database enables true incremental synthesis and much faster design and verification turnaround time
Constraint-functionality separation (CFS) enables efficient reuse across multiple applications and process technologies
Fast hardware models (FHMs) accelerate verification and enable early hardware/software co-development


Features/Benefits

Accepts widest-range of C/C++/SystemC coding styles and constructs, including templates, classes, user-defined types, and certain types of pointers
Embedded Encounter® RTL Compiler delivers consistently accurate timing and area information during the entire high-level synthesis process, resulting in signoff-quality RTL for all types of designs
BST database tracks evolution of design-data starting from C/C++/SystemC source files all the way to physical implementation, enabling direct mapping of physical design data back to RTL as well as the original C/C++/SystemC source code
CFS keeps functionality, communication, and design constraints all independent, enabling designers to keep their source code “golden” and retarget new applications by only changing communication/design constraints
Approximately-timed FHMs generated in SystemC simulate 80-90% as fast as the original untimed input model, enabling fast verification and early hardware-software co-development
Interactive GUI provides a complete environment for synthesis, analysis, and debug, giving users excellent control and visibility over the high-level synthesis process




Cadence C-to-Silicon Compiler (CtoS) is next-generation high-level synthesis (HLS) software for automatically generating synthesizable Verilog RTL from C++/SystemC. Companies recently adopting CtoS, such as Hitachi and Renesas, have seen their designers able to generate high-quality RTL code with less than 10% of the effort required to write RTL “from-scratch”, fewer bugs, and reduced verification-time. Unlike previous-generation HLS tools, C-to-Silicon Compiler’s underlying technology is general purpose. Previous-generation HLS tools had been limited to supporting either control-intensive or datapath-intensive circuits; CtoS supports both. CtoS is also the first HLS technology to allow incremental (“ECO”) synthesis from source-code changes. Any resulting changes to the output RTL reflect only those changes mandated by the designer; the rest of the RTL remains untouched, minimizing re-verification effort.

The added capabilities and performance of CtoS versus previous generation HLS tools came as a result of two key innovations: Embedded Logic Synthesis (ELS), and a Behavior-Structure-Timing (BST) database. With ELS, CtoS runs Cadence RTL Compiler logic-synthesis “under-the-hood,” enabling context-specific circuit-timing estimates, critical for high-quality results in mixed-control/datapath designs. The BST database lets CtoS record every data-transformation and optimization-decision during the HLS process, enabling controlled, precise incremental synthesis.

HLS has been a “holy grail” of EDA for nearly 20 years. With major contributions from world synthesis experts at Cadence Berkeley Labs, and $20M+ IR&D investment, Cadence managed to invent new technology to solve these challenges and lead the industry toward a new IC design paradigm. In 2008 these innovations were proven-out at several large semiconductor companies using production designs.

ald_syn_cad

Thanks so much baby!
It is in the third sale grade in the HLS market. #1 is Catapult, #2 is Forte.
I need Calypto SLEC and PowerPro.

phoenixson

just versus HLS of synopsys.

ald_syn_cad

Synopsys Synphony C is at the end of the list. For more info refer to Deepchip.com or eetimes.com

sinva

回复 1# nerohark


   is there any crk?

ostora2

thanks you very much

ostora2

is ths any crack ?

doyoucool

好用吗，可以吗。

77xzlheo

哪位达人给出crack啊？我悬赏1500积分！

ald_syn_cad

Get this.
This is also working for:
CTOS-12.10.100:
http://pan.baidu.com/netdisk/singlepublic?fid=576676_121348588
If the lic did not work, just add below lines to the top of License file:

SERVER your_host_name ANY
DAEMON cdslmd /home/Cadence/Install/License/tools/bin/cdslmd