|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
工作地点:北京
有意者请发送简历到feng.xuan@gmail.com
要求:
The ideal candidate will have a Master's degree, along with a theoretical background and practical experience of 3 years or more in the mixed-signal IC design industry. Competency in digital design, system implementation, and understanding fundamental digital circuits including finite state machines, synchronous/asynchronous de-bounce and de-glitch circuitry, clock and reset strategies, binary/gray code encoding, and serial communication interfaces (I2C/SPI) is necessary.
This engineer must be capable of RTL design using Verilog/VHDL, verification using automatic checking testbenches, code coverage analysis, synthesis, scan insertion, place and route, logical equivalence checking, static timing analysis, and interfacing with Cadence analog tools such as Virtuoso. |
|